{PORT B}{ˆHOST INTERFACE}{ˆHI}

	Port B is a dual-purpose I/O port that can be used as 15 general-purpos 
pins individually configurable as either inputs or outputs, or as an 8-bit
bidirectional host interface ({HI}).

{HOST INTERFACE} ({HI})

	The {HI} is a byte-wide, full duplex, double-buffered, parallel port which
may be connected directly to the data bus of a host processor. The
hostprocessor may be any of a number of industry standard microcomputers or
microprocessors, another DSP, or DMA hardware because this interface
lookslike static memory. The {HI} is asynchronous and consists of two banks of
registers - one bank accessible to the host processor and a second bank
accessible to the DSP CPU. A brief description of the {HI} features is
presented in the following listing:

Speed
	8 MByte/Sec Burst Data Transfert Rate
	1.71 Million Word/Sec Interrupt Driven Data Transfer Rate (This is the
	maximum interrupt rate for the DSP56000/DSP56001 running at 20.5 MHz -
	i.e., one interrupt every six instruction cycles.)

Interface - DSP CPU Side
	Mapping:   Three X: Memory Locations

	Data Word:	24 Bits

	Transfer Modes:
		DSP to Host
		Host to DSP
		Host Command

	Handshaking Protocols:
		Softwware Polled
		Interrupt Driven (Fast or Long)
		Direct Memory Access

Instructions:
	Memory-mapped registers allow the standard MOVE instruction to be used.

	Special MOVEP instruction provides for I/O service capability using fast
interrupts.

	Bit addressing instructions ({BCHG}, {BCLR}, {BSET}, {BTST}, {JCLR}, {JSCLR}, {JSET},
{JSSET}) simplify I/O service routines.

	I/O short addressing provides faster execution with fewer instruction
words.

Interface - Host Side

	Mapping:
		Eight Consecutive Memory Locations
		Memory-Mapped Peripheral for Microprocessors, DMA controllers, etc..

	Data Word:	8 Bits

	Transfer Modes:
		DSP to Host
		Host to DSP
		Host Command
		Mixed 8-, 16-, and 24-Bit Data Transfers

	Handshaking Protocols:
		Software Polled
		Interrupt Driven - Compatible with MC680x0
		Cycle stealing DMA with initialization

	Dedicated Interrupts:
		Separate Interrupt Vectors for Each Interrupt Source

		Special host commands force DSP CPU interrupts under host processor
		control, which are useful for:
			Real-Time production Diagnostics
			Debugging Window for Program Development
			Host Control Protocols and DMA Setup

The {HI} registers can be divided vertically down the middle into registers
visible to the host processor on the left and registers visible to the DSP
on the right. They can also be divided horizontally into control at the top,
DSP-to-host data transfer in the middle ({HTX}, RXH, RXM, and RXL), and
host-to-DSP data transfer at the bottom (TXH, TXM, TXL, and {HRX}).

Host Interface - DSP CPU Viewpoint

	The DSP views the {HI} as a memory-mapped peripheral occupying three
24-bit words in data memory space. The DSP may use the {HI} as a normal
memory-mapped peripheral, using either standard polled or interrupt
programming techniques. Separate transmit and receive data registers are
double buffered to allow the DSP and host processor to efficiently transfer
data at high speed. Memory mapping allows DSP CPU communication with the {HI}
registers to be accomplished using standard instructions and addressing
modes. In addition, the MOVEP instruction allows {HI}-to-memory and
memory-to-{HI} data transfers without going through an intermediate register.
Both hardware and software reset disable the {HI} and change port B to general
purpose I/O with all pins designated as inputs.

Programming Model - DSP CPU Viewpoint

	The {HI} has two programming models - one for the DSP programmer and one
for the host processor programmer. In most cases, the notation used reflects
the DSP perspective. There are three registers: 1) a control register ({HCR}),
2) a status register ({HSR}), and 3) a data transmit/receive register
({HTX}/{HRX}). These registers can only be accessed by the DSP56000/DSP56001;
they can not be accessed by the hostprocessor.

The following paragraph describes the purpose and operation of each bit in
each register of the {HI} visible to the DSP CPU. the effects of the different
types of reset on these registers are shown. A brief discussion of
interrupts and operation of the DSP side of the {HI} complete the programming
model from the DSP viewpoint.

REGISTER CONTENTS AFTER RESET:

	Table shows the results of four reset types on bits in each of the {HI}
registers seen by the DSP CPU. The hardware reset (HW) is caused by the
~RESET signal; the software reset (SW) is caused by executing the {RESET}
instruction; the individual reset (IR) is caused by clearing the BPC
register bit 0; and the stop reset (ST) is caused by executing the {STOP}
instruction.

	+----------+----------+-------------------------------+
	|          |          |           Reset Type          |
	| Register | Register +-------+-------+-------+-------+
	|   Name   |   Data   |   HW  |   SW  |   IR  |   ST  |
	|          |          | Reset | Reset | Reset | Reset |
	+----------+----------+-------+-------+-------+-------+
	|          | HF(3-2)  |   0   |   0   |  ---  |  ---  |
	|          +----------+-------+-------+-------+-------+
	|          | {HCIE}     |   0   |   0   |  ---  |  ---  |
	|   {HCR}    +----------+-------+-------+-------+-------+
	|          | {HTIE}     |   0   |   0   |  ---  |  ---  |
	|          +----------+-------+-------+-------+-------+
	|          | {HRIE}     |   0   |   0   |  ---  |  ---  |
	+----------+----------+-------+-------+-------+-------+
	|          | {DMA}      |   0   |   0   |   0   |   0   |
	|          +----------+-------+-------+-------+-------+
	|          | {HCP}      |   0   |   0   |   0   |   0   |
	|   {HSR}    +----------+-------+-------+-------+-------+
	|          | {HTDE}     |   1   |   1   |   1   |   1   |
	|          +----------+-------+-------+-------+-------+
	|          | {HRDF}     |   0   |   0   |   0   |   0   |
	+----------+----------+-------+-------+-------+-------+
	|   {HRX}    | {HRX}(23-0)|  ---  |  ---  |  ---  |  ---  |
	+----------+----------+-------+-------+-------+-------+
	|   {HTX}    | {HTX}(23-0)|  ---  |  ---  |  ---  |  ---  |
	+----------+----------+-------+-------+-------+-------+

HOST INTERFACE DSP CPU INTERRUPTS.

	The {HI} may request interrupt service from either the DSP or the host
processor. the DSP CPU interrupts are internal and do not require the use of
an external interrupt pin. When the appropriate mask bit in the {HCR} is set,
an interrupt condition caused by the host processor sets the appropriate bit
in the {HSR}, which generates an interrupt request to the DSP CPU. The DSP
acknoledges interrupts caused by the host processor by jumping to the
appropriate interrupt service routine. The three possible interrupts are 1)
receive data register full, 2) transmit data register empty, and 3) host
command. The host command can access any interrupt vector in the interrupt
interrupt vector table although it has a set of vectors reserved for host
command use. The DSP interrupt service routine must read or write the
appropriate {HI} register (i.e., clearing {HRDF} or {HTDE}, for example) to clear
the interrupt. In the case of host command interrupts, the interrupt
acknowledge from the program controller will clear the pending interrupt
condition.

HOST PORT USAGE CONSIDERATIONS --- DSP SIDE

	Careful synchronization is required when reading multibit registers that
are written by another asynchronous system.

This is a common problem when two asynchronous systems are connected. The
situation exists in the {HI}. However, if the {HI} is used in the way it was
designed, proper operation is guaranteed.{DMA},{HF1},{HF0},{HCP},{HTDE}, {HRDF} status
bits are set or cleared by the host processorside of the interface. These
bits are individually synchronized to the DSPclock. The only system problem
with reading status occurs with {HF1} and {HF0} if theyare encoded as a pair --
e.g., the four combinations (00,01,10, and 11) each have significance. This
problem occurs because there is a very small probability that the DSP will
read the status bits during the transition. The solution to this potential
problem is to read the bits twice forconsensus.


{HOST CONTROL REGISTER} ({HCR}):{ˆHRIE}{ˆHTIE}{ˆHCIE}{ˆHF2}{ˆHF3}

	The {HCR} is an 8-bit read/write control register used by the DSP to
control the {HI} interrupts and flags. The {HCR} cannot be accessed by the host
processor. The {HCR} occupies the low-order byte of the internal data bus; the
high-order portion is zero filled. {HCR} is a read/write register to allow
individual control register bits to be set or cleared. Any reserved bits are
read as zeros and should be programmed as zeros for future compatibility.
The bit manipulation instructions are useful for accessing the individual
bits. The contents of {HCR} are cleared on hardware or software reset. The
control bits are described in the following paragraphs.

{Host Receive Interrupt Enable} ({HRIE}) {HCR} Bit 0:

	The {HRIE} bit is used to enablea DSP interrupt when the host receive data
full ({HRDF}) status bit in the host status register ({HSR}) is set. When {HRIE}
is cleared, {HRDF} interrupts are disabled. When {HRIE} is set, a host receive
data interrupt request will occur if {HRDF} is set. Hardware and software
resets clear {HRIE}.

{Host Transmit Interrupt Enable} ({HTIE}) {HCR} Bit 1:

	The {HTIE} bit is used to enable a DSP interrupt when the host transmit
data empty ({HTDE}) status bit in the {HSR} is set. When {HTIE} is cleared, {HTDE}
interrupts are disabled. When {HTIE} is set, a host transmit data interrupt
request will occur if {HTDE} is set. Hardware and software resets clear {HTIE}.

{Host Command Interrupt Enable} ({HCIE}) {HCR} Bit 2:
	The {HCIE} bit is used to enable a vectored DSP interrupt when the host
command pending ({HCP}) status bit in the {HSR} is set. When {HCIE} is cleared,
{HCP} interupts are disabled. When {HCIE} is set, a host command interrupt
request will occur if {HCP} is set. The starting address of this interrupt is
determined by the host vector (HV). Hardware and software resets clear {HCIE}.

{Host Flag 2} ({HF2}) {HCR} Bit 3:

	The {HF2} bit is used as a general-purpose flag for DSP-to-host
communication. {HF2} may be set or cleared by the DSP. {HF2} is visible in the
interrupt status register (ISR) on the host processor side. Hardware and
software resets clear {HF2}.

NOTE:	There are four host flags: two used by the host to signal the DSP
({HF0} and {HF1}) and two used by the DSP to signal the host processor ({HF2} and
{HF3}).These flags are not designated for any specific purpose but are
general-purpose flags. The host flags do not cause interrupts; they must be
polled to see if they have changed. These flagscan be used individually or
as encoded pairs.

{Host Flag 3} ({HF3}) {HCR} Bit 4:

	The {HF3} bit is used as a general-purpose flag for DSP-to-host
communication. {HF3} may be set or cleared by the DSP. {HF3} is visible in the
ISR on the host processor side. Hardware and software resets clear {HF3}.

{Reserved Bits} ({HCR} Bits 5, 6, and 7):

	These unused bits are reserved for future expansion and should be
written with zeros for upward compatibility.


{HOST STATUS REGISTER} ({HSR}):{ˆHRDF}{ˆHTDE}{ˆHCP}{ˆHF0}{ˆHF1}{ˆDMA}
	The {HSR} is an 8-bit read only status register used by the DSP to
interrogate status and flags of the {HI}. It can not be directly accessed by
the host processor. When the {HSR} is read to the internal data bus, the
register contents occupy the low-order byte of the data bus; the high-order
portion is zero filled. The status bits are described in the following
paragraphs.

{Host Receive Data Full} ({HRDF}) {HSR} Bit 0:
	The {HRDF} bit indicates that the host receive data register ({HRX})
contains data from the host processor. {HRDF} is set when data is transferred
from the TXH:TXM:TXL registers to the {HRX} register. {HRDF} is cleared when {HRX}
is read by the DSP. {HRDF} can also be cleared by the host processor using the
initialize function. Hardware, software, individual and {STOP} resets clear
{HRDF}.

{Host Transmit Data Empty} ({HTDE}) {HSR} Bit 1:

	The {HTDE} bit indicates that the Host Transmit Data Register ({HTX}) is
empty and can be written by the DSP. {HTDE} is set when the {HTX} register is
transferred to the RXH:RXM:RXL registers. {HTDE} is cleared when {HTX} is
written by the DSP. {HTDE} can also be set by the host processor using the
initialise function. Hardware, software, individual, and {STOP} resets set
{HTDE}.

{Host Command Pending} ({HCP}) {HSR} Bit 2:

	The {HCP} bit indicates that the host has set the HC bit and that a host
command interrupt is pending. The {HCP} bit reflects the status of the HC bit
in the command vector register (CVR). HC and {HCP} are cleared by the DSP
exception hardware when the exception is taken. The host can clear HC, which
also clears {HCP}. Hardware, software, individual, and {STOP} resets clear {HCP}.

{Host Flag 0} ({HF0}) {HSR} Bit 3:

	The {HF0} bit in the {HSR} indicates the state of host flag 0 in the ICR on
the host processor side. {HF0} can only be changed by the host processor.
Hardware, software, individual, and {STOP} resets clear {HF0}.

{Host Flag 1} ({HF1}) {HSR} Bit 4:

	The {HF1} bit in the {HSR} indicates the state of host flag 1 in the ICR on
the host processor side. {HF1} can only be changed by the host processor.
Hardware, software, individual, and {STOP} resets clear {HF1}.

{Reserved Bits} ({HSR} Bits 5 and 6):

	These status bits are reserved for future expansion and reads as zero
during DSP read operations.

{DMA Status} ({DMA}) {HSR} Bit 7:

	The {DMA} bit indicates that the host processor has enabled the {DMA} mode of
the {HI} by setting HM1 or HM0 to one. When {DMA} bit is zero, it indicates that
the {DMA} mode is disabled by the HM0 and HM1 bits in the ICR and that no {DMA}
operations are pending. When {DMA} is set, the {DMA} mode has been enabled by one
or more of the host mode bits being set to one.The channel not in use can be
used for polled or interrupt operation bythe DSP. Hardware, software,
individual, and {STOP} resets clear the {DMA} bit.


{HOST RECEIVE DATA REGISTER} ({HRX}):
	The {HRX} register is used for host-to-DSP data transfers.The {HRX} register
is viewed as a 24-bit read-only register by the DSP CPU. The {HRX} register is
loaded with 24-bit data from the transmit data registers (TXH:TXM:TXL) on
the host processor side when both the transmit data register empty TXDE on
the host processor side and DSP host receive data full ({HRDF}) bits are
cleared. This transfer operations sets TXDE and {HRDF}. The {HRX} register
contains valid data when the {HRDF} bit is set. Reading {HRX} clears {HRDF}. The
DSP may program the {HRIE} bit to cause a host receive data interrupt when
{HRDF} is set. Resets do not affect {HRX}.


{HOST TRANSMIT DATA REGISTER} ({HTX}):

	The {HTX} register is used for DSP-to-host data transfers. The {HTX}
register is viewed as a 24-bit write-only register by the DSP CPU. Writing
the {HTX} register clears {HTDE}. The DSP may program the {HTIE} bit to cause a
host transmit data interrupt when {HTDE} is set. The {HTX} register is
transfered as a 24-bit data to the receive byte registers (RXH:RXM:RXL) if
both the {HTDE} bit (DSP CPU side) and receive data full (RXDF) status bits
(host processor side are cleared. This transfer operation sets RXDF and
{HTDE}. Data should not be written to the {HTX} until {HTDE} is set to prevent the
previous data from being overwritten. Resets do not affect {HTX}.


