A method and apparatus for enhancing the speed of operation of a computer consists of providing a cache memory which is faster than the computer's main memory, disabling the computer's main microprocessor, and replacing it with a microprocessor with a faster clock cycle time. A portion of the program stored in the main memory is stored in the cache memory. The addresses of the portion of the main memory stored in the cache memory are noted in a tag RAM. Upon each addressing sequence during the execution of a program, the tag RAM is examined to determine if the addressed located is stored in the cache memory. If the stored location is identified in the tag RAM, it is retrieved from the cache memory at high-speed. Otherwise, the data in the address location is retrieved from main memory at a slower speed and written into the cache memory so that subsequent accesses may be made at high-speed.

                  TABLE I
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    PAL Control Signals
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    PAL 64
    PCK:   Processor Clock. Depending on the mode of
           the system (high speed or synchronous with
           slower APPLE clock) this clock will fluctuate
           between 1 MHz and 3.59 MHz.
    WRT:   Cache write signal. Low when writing to Cache
           memory 48, 50.
    CEN:   Cache output enable. Low when processor 42
           is reading Cache memory 48, 50.
    EXW:   External Write signal. Asserted when a write
           to the APPLE bus 47 is required. Propagates
           through to PALX where the actual APPLE write
           is synchronized. This signal initiates the process.
    TAG:   Cache tag signal. This signal is asserted
           when cache RAM 48, 50 is written to.
    CRD:   Cache read signal. This signal is asserted
           when cache RAM 48, 50 is read from.
    FF0:   Timing signal flip-flop. This signal, combined
           with FF1, stops and starts PCK for transitions
           between synchronous 1 MHz operation and asyn-
           chronous 3.59 MHz operation.
    CLR:   Initiates slow down of PCK from 3.59 MHz to 1
           MHz. Also latches address and data into buf-
           fers 56, 58 and 46 for writes to the APPLE
           bus 47, 54 which are later enabled onto the
           APPLE bus during the next phase 0 clock cycle.
           If data is latched into the first stage buf-
           fers 56, 58 and 46 and a subsequent write
           occurs before the next phase 0, the processor
           will stop until the next phase 0 before CLR
           can latch the new data into the buffer.
    DL1:   Used for synchronization during clock changes.
           No signals may be generated unless DL1 and
           DL2 are of the same state. When the clock
           rate is to change, these two signals will
           sequentially change states. Other signals in
           the PAL's look at these two signals to deter-
           mine whether writes/reads are out of cache or
           the APPLE bus 47, 54.
    DL2:   See DL1.
    0AN:   Same as 0AN on PAL 66.
    7MN:   Inverted 7.18 MHz clock from the APPLE bus.
           This clock is divided by two internally pro-
           ducing the 3.59 MHz clock used for high-speed
           operations.
    HLD:   When CLR is generated, HLD holds CLR for one
           following phase 0 clock cycle.
    4M:    High speed clock. This is the divided by two
           versions of 7MN described above. This is
           actually a misnomer since the actual frequency
           present at this pin is 3.59 MHz.
    RWN:   Read/Write signal output from microprocessor 42.
    FF1:   See FF0.
    MCH:   Match signal from comparator 74. This signal
           is asserted low by the comparator whenever
           tag memory 68, 70 matches the current requested
           memory byte. If the tag bits match, MCH may
           still be disabled if the location is not a
           valid cache location as determined by MENABN
           produced by MEN of PAL 80.
    2MN:   Used for proper synchronization of DL1 and DL2.
    PAL 66
    TMO:   Clock for disabling the system. This signal
           gates the BDDIS* signal from PAL 78 into a
           latch which completely removes the system
           from operation thus releasing all address and
           data lines. Allows the Direct Memory Access
           line (pin 22) on the APPLE bus to float high
           enabling the APPLE's normal 6502 microproces-
           sor to operate. Any time pin 22 is low, the
           APPLE 6052 is completely disabled, floating
           all of its address and data lines which is
           the method in which the present system takes
           control of the APPLE.
    XWR:   This signal takes the place of the normal
           APPLE WR* signal (pin 18 on the APPLE bus).
           When an actual write to the APPLE bus occurs,
           this signal drops low. This signal is dis-
           abled when DMA is not asserted.
    REN:   ROM Enable: The presence of ROM 84 is indi-
           cated by the assertion of this signal and is
           only present while the system is determining
           the mode of operation. It disallows the sys-
           tem to cache memory from the high address
           space which is where the ROM image is initially
           located (thus overlaying the APPLE operating
           system ROM's). This is necessary since the
           cache RAM is undefined upon power-up and it
           allows the power-up software to define all of
           the cache before normal operation. After the
           cache initialization, the system creates a
           copy of itself in normal APPLE RAM at address
           $1000 (hex) and transfers execution to there.
           Normal operation starts, and this signal is
           asserted false, thus allowing the system to
           cache high memory.
    DOE:   Data Bus Buffer Output Enable: This signal
           enables the data bus output buffers 44, 46
           for writes to the APPLE bus 47.
    BRE:   Data Bus Buffer Read Output Enable: For reads
           from the APPLE bus, this signal enables the
           output buffer.
    OAN:   Maser Asynchronous 3.59 MHz clock which is
           derived by dividing the APPLE 7.18 MHz clock by 2.
    FF1:   See FF1 of PAL 64.
    7MN:   See 7MN of PAL 64.
    EXW:   See EXW of PAL 64.
    FF0:   See FF0 of PAL 64.
    RST:   Reset signal from APPLE bus. Causes the sys-
           tem to begin reading its on-board ROM 84 with-
           out caching memory, thus enabling the software
           to initialize the cache memory.
    INQ:   I/OSTRB* signal from APPLE bus. REN is enabled
           by a reset and is held until this signal appears.
    DMA:   Allows signals to be generated. When the
           system is disabled, this signal is asserted
           low causing outputs from this PAL to the APPLE
           bus to stop.
    CRD:   Latched version of CRD from PAL 64. Causes
           generation of read signals from this PAL 66
           and is latched through by the 4MN clock.
    0ON:   Inverted phase 0 from APPLE bus.
    A11:   Inverted Address line 11 from microprocessor 42.
    CFD:   When gated with EXW generates a timing pulse
           for system disable.
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