ftp.funet.fi:/pub/cbm/schematics/computers/p500/

4256041-01of15.gif 1998-09-28 346636: Commodore 500 µP, address & data buffers, arbitration logic
4256041-02of15.gif 1998-09-27 264513: system decode & buffer control
4256041-03of15.gif 1998-09-28 292293: VIC; video memory; video bus buffers
4256041-04of15.gif 1998-09-27 192900: SID; 192k DRAM array refresh logic
4256041-05of15.gif 1998-09-28 279736: 192k DRAM address mux & control
4256041-06of15.gif 1998-09-27 238991: 192k*8 DRAM array [64k standard, 128k optional]
4256041-07of15.gif 1998-09-28 223503: 64k DRAM array and address mux
4256041-08of15.gif 1998-09-28 194905: system ROM/RAM array
4256041-09of15.gif 1998-09-28 273583: gameport interface; keyboard interface; RS232C interface
4256041-10of15.gif 1998-09-27 295118: interrupt prioritization; IEEE488 interface; user/game port interface
4256041-11of15.gif 1998-09-28 258517: cassette i/f port
4256041-12of15.gif 1998-09-27 193891: main oscillators & PLL
4256041-13of15.gif 1998-09-28 150690: video output circuit
4256041-14of15.gif 1998-09-27 289443: [List of power filter capacitors for each IC]
4256041-15of15.gif 1998-09-28 211721: [FPLA logic equations]
README 1998-10-20 920: Information about the Commodore 500 a.k.a. PET II.
keyboard.txt 1999-07-30 3512: Commodore P500 Keyboard Schematic. Composed by Tony Duell <ard@p850ug1.demon.co.uk>.

ftp://ftp.funet.fi/pub/cbm/schematics/computers/p500/